SH Consulting Vietnam

Tóm tắt công việc

- Create plan and strategy for functional verification of IPs (e.g. RISC CPU, Interrupt controller, Interconnect Fabric, Peripherals, etc.)
- Create test cases and test patterns according to the verification plan and strategy
- Create verification environment (e.g. test bench)
- Execute verification and analyze failures
- Work with designers to find and fix bugs of IPs

- 2+ years’ experience in logic design using Verilog / System Verilog
- Experience in logic simulation
- Experience in programming
- Experience in scripting language

Preferred Experience / Knowledge:
- Assembler and C/C++
- Scripting Language sh, csh, Perl, etc.
- Modelsim or VCS
- Universal Verification Methodology (UVM)
- Open Verification Methodology (OVM)
- Verification Methodology Manual (VMM)
- SystemVerilog Assertions (SVA)
- Random test pattern generation
- Functional model design using Verilog, SystemVerilog or SystemC
- CPU, Interrupt controller, Cache, MMU, Bus (AXI, AHB, APB), etc.

* Benefits:
- Salary package: competitive and negotiable
- Applicable for all normal benefits: insurances, 13th salary, annual outing trip, team building activities…
- Have chance to go abroad: US, Japan.